1. Field of the Invention
The present invention generally relates to a semiconductor package, and more particularly to a semiconductor package including two stacked chips, a non-conductive adhesive disposed between the stacked chips, and supporting balls for defining the necessary space of bonding wires, wherein the adherent area between the non-conductive adhesive and the upper chip is larger than 90% of the area of lower surface of the upper chip, thereby reducing the concentration of stress after an encapsulating process, and further avoiding the chip crack and increasing the yield of the semiconductor package.
2. Description of the Related Art
With ever increasing demands for miniaturization and high operating speeds, a multi-chip module is increasingly attractive in a variety of electronics. The multi-chip module is a module or package capable of supporting more than one chip on a single semiconductor package. For example, a multi-chip memory package includes several memory chips on a commonly shared substrate, which provides size advantages, and increases the storage capacity of the package. Furthermore, a multi-chip package has high operational speed and can decrease the interconnection distance between IC chips, thereby reducing signal delays and access times. In addition, a multi-chip package has an integrally operational function, because it can combine chips having different functions, such as memory chip, logic chip, microprocessor, etc. in a single semiconductor package.
Recently, as described below, two chips were stacked using a mainly conventional semiconductor package. According to the first conventional semiconductor package 2, the first conventional semiconductor package 2 includes a substrate 10, a lower chip 20, a dummy chip 30 and an upper chip 40. Referring to FIG. 1, the lower chip 20 is mounted on the substrate 10 by means of an adhesive 22, and two edges of the upper surface 28 of the lower chip 20 are provided with a plurality of aluminum pads 24, which are electrically connected to a plurality of pads 12 of the substrate 10 through a plurality of first bonding wires 26. Referring to FIG. 2, the dummy chip 30 is mounted on the lower chip 20 by means of an adhesive 32, and defines the necessary space of the first bonding wires 26 such as above a height (H) of 5 mils. Referring to FIG. 3, the upper chip 40 is mounted on the dummy chip 30 by means of an adhesive 42, and the upper surface 48 of the upper chip 40 are provided with a plurality of aluminum pads 44, which are electrically connected to the pads 12 of the substrate 10 through a plurality of second bonding wires 46, such that the two chips 20, 40 are stacked on the substrate 10. However, the first conventional semiconductor package 2 requires a higher manufacturing cost and longer packaging time. Furthermore, there is a mismatch between the expansion coefficients of the dummy chip and the adhesive, and thus the stress of an interface between the dummy chip and the adhesive is increased after an encapsulating process, which can result in chip crack, thus reducing the yield of semiconductor package. The yield of the semiconductor package 2 generally ranges between 30% and 40%.
Furthermore, the second conventional semiconductor package 50 is substantially similar to the first conventional semiconductor package 2. The second conventional semiconductor package 50 includes a substrate 60, a lower chip 70 and an upper chip 90. Referring to FIG. 4, a plurality of aluminum pads 74 are only disposed on the same edge of the upper surface 78 of the lower chip 70. Referring to FIG. 5, the lower chip 70 is mounted on the substrate 60 by means of an adhesive 72, and the aluminum pads 74 of the lower chip 70 are electrically connected to a plurality of pads 62 of the substrate 60 through a plurality of first bonding wires 76. Then, the upper chip 90 is mounted on the lower chip 70 by means of an adhesive 92, and is stacked on the lower chip 70 by using a step-stacked manner. Finally, the upper surface 98 of the upper chip 90 are provided with a plurality of aluminum pads 94, which are electrically connected to the pads 62 of the substrate 60 through a plurality of second bonding wires 96, such that the two chips 70, 90 are stacked on the substrate 60. However, chips formed by this step-stack manner have to be specially designed and are distinctly different from the common chips; therefore, they may not be easy to acquire, and their cost may be increased. Furthermore, a package includes at least two stacked chips so by using this step-stacked manner, each additional chip must be reduced in size, thus the cost of the chip is increased.
In addition, Taiwan Patent Publication Number 442,876, entitled “Multi-chip Package”, discloses a stacked structure of a semiconductor package. The semiconductor package includes a chip carrier, a plurality of conductive bumps, a plurality of bonding wires, a plurality of chips (e.g. a lower chip and an upper chip) and an adhesive layer. The lower chip is disposed on the chip carrier. The conductive bumps are disposed on the lower chip. The upper chip is disposed on the lower chip by means of the adhesive layer, and each conductive bump has a cylindrical protrusion for supporting the upper chip. However, the adhesive layer is not a conductive adhesive layer, and the cylindrical protrusion is made of a conductive material, such that the adhesive layer cannot fully isolate the upper chip from the lower chip. Furthermore, the cylindrical protrusion possibly damages the surface of the upper chip.
In addition, Taiwan Patent Publication Number 510,573, entitled “Multi-chip Stacked In A Semiconductor Package”, discloses a stacked structure of a semiconductor package. The semiconductor package includes an encapsulant, a plurality of chips, a chip carrier, a plurality of metal traces and a glass fiber epoxy resin layer. The chips are encapsulated in the encapsulant, and each chip has an upper surface, a low surface and a plurality of bonding pads formed on the upper surface. The chip carrier, such as a substrate or a leadframe, is used for mounting the stacked chips. The metal traces are encapsulated in the encapsulant for electrically connecting the bonding pads of the chip to the chip carrier. The glass fiber epoxy resin layer is located between the two chips for mounting two stacked chips. However, the glass fiber epoxy resin layer is made of soft material, and thus the glass fiber epoxy resin layer cannot fully define the necessary space of the bonding wires (i.e. metal traces), such as above a height of 5 mils.
Accordingly, there exists a need for a semiconductor package capable of solving the above-mentioned problem.